1. Field of the Invention
The present invention relates to internal clock generating circuitry provided with a phase locked loop or PLL built therein for testing an integrated circuit that can operate with a high-speed clock, for supplying an internal clock to the integrated circuit.
2. Description of the Prior Art
Referring next to FIG. 17, a schematic circuit diagram is illustrated showing the structure of prior art internal clock generating circuitry having a PLL built therein and a testing function. In the figure, reference numeral 101 denotes a phase comparator for comparing the phases of two input voltages with each other and for generating a voltage VCNT corresponding to the phase difference, numeral 102 denotes a VCO for generating a clock signal having a frequency corresponding to the output voltage VCNT from the phase comparator 101, numeral 103 denotes a normal clock generating circuit for generating a plurality of normal clock signals from the clock signal, as an original signal applied thereto, from the VCO 102 and for furnishing a feedback signal to the phase comparator 101, numeral 104 denotes a selector for switching between the plurality of normal clock signals from the normal clock generating circuit 103 and a plurality of test clock signals described below, numeral 105 denotes a voltage controlled delay circuit for generating a clock signal while controlling a delay to be provided for the clock signal according to a control voltage applied thereto, numeral 106 denotes a test clock generating circuit for generating the plurality of test clock signals from the clock signal, as an original signal applied thereto, from the voltage controlled delay circuit 105, numeral 107 denotes an inverter, and numeral 108 denotes a tristate gate having an inverting function. The VCO 102 generates a clock signal whose frequency is adjusted according to the voltage VCNT from the phase comparator 101 so that the phase difference between the phases of the two input clock signals applied to the phase comparator 101 becomes small. In addition, reference strings Xin and Xout denote input terminals to which signals are applied from outside the internal clock generating circuitry, and reference character A denotes a control signal applied in common to both the selector 104 and the tristate gate 103.
Referring next to FIG. 18, a schematic circuit diagram is illustrated showing the transistor-level structure of the VCO 102. Each of a plurality of transistor groups 110a to 110e, each of which is surrounded by a dashed line in the figure, constitutes an inverter. Changing the control voltage VCNT can control a current flowing through each of the plurality of transistor groups that constitutes each of the plurality of inverters 110a to 110e, thus delaying the transmission of a signal between any two adjacent inverters. In FIG. 18, reference characters a, b, c, d, and e denote output signals from the plurality of inverters, respectively. FIG. 19 is a schematic circuit diagram showing the transistor-level structure of the voltage controlled delay circuit 105. As can be seen from the figure, the voltage controlled delay circuit 105 can be constructed by connecting two VCOs, as shown in FIG. 18, in each of which the loop is, however, opened, so that a plurality of inverters 111a to 111j are connected in series. Even in this circuit, changing the control voltage VCNT can control a current flowing through each of the plurality of transistor groups that constitutes each of the plurality of inverters 111a to 111j, thus delaying a clock signal applied to the input terminal Xin by a time delay corresponding to the control voltage while the clock signal travels between any two adjacent inverters.
Referring next to FIG. 20, an example is illustrated of the normal clock generating circuit that generates a plurality of normal clock signals based on the clock signal from the VCO. In the figure, reference numerals 120, 121, 122, and 123 denote path transistors, numerals 124, 125, 126, 127, 128, and 129 denote inverters, numeral 130 denotes a NAND gate, and numerals 131 and 132 denotes AND gates. In addition, reference characters b, c, and d denote the same signals as the output signals b, c, and d from the VCO as shown in FIG. 18. A circuit surrounded by a dashed line is a frequency divider for dividing the frequency of a clock signal applied thereto to generate a clock having a frequency one-half times as large as that of the input clock signal. Since the divider is a well known device in this field, the detailed description of the divider will be omitted hereinafter.
Under normal conditions, the control signal A at a given level is applied to both the tristate gate 108 and the selector 104 so that the tristate gate 108 is brought into conduction and the selector 104 selects the plurality of normal clocks 1 to 3 as a plurality of internal clocks 1 to 3, respectively. As a result, the clock signal applied to the input terminal Xin is furnished, by way of the other input terminal Xout, to the phase comparator 101. The phase comparator 101 compares the phase of the clock signal applied to the input terminal Xin with that of the clock signal fed back thereto from the normal clock generating circuit 103, and then generates and furnishes a voltage VCNT corresponding to the phase difference between those clock signals to the VCO 102. The VCO 102 oscillates according to the voltage VCNT to supply an original clock signal to the normal clock generating circuit 103 to allow the normal clock generating circuit to generate the plurality of normal clock signals. The normal clock generating circuit 103 divides the frequency of the input original clock signal to generate the plurality of normal clock signals, and then generates and feeds a clock signal whose frequency is one-quarter of that of the original clock signal back to the phase comparator 101. In this manner, the normal clock generating circuit 103 generates the plurality of normal clock signals 1 to 3 in cooperation with the phase comparator 101, and the VCO 102, which constitute a feedback loop together with the normal clock generating circuit 103. The selector 104 delivers the plurality of normal clock signals 1 to 3, as the internal clock signals 1 to 3.
Next, a description will be made as to the operation of each component of the internal clock generating circuitry under normal conditions. FIG. 21 is a timing chart showing the waveforms of a plurality of clock signals applied to the circuitry and generated in the circuitry under normal conditions. As shown in FIG. 18, the VCO 102 determines a oscillating frequency based on the delays which the plurality of inverters included with the VCO 102 provide according to the voltage VCNT from the phase comparator 101. The output signals b, c, d, and e from the respective stages of the VCO 102 are delayed with respect to the output signals a, b, c, and d by a given time delay, respectively. In addition, each of the output signals b, c, d, and e is the inverse of each of the output signals a, b, c, and d. When the output signals b, c, and d from the VCO 102 are applied to the signals lines b, c, and d as shown in FIG. 20, respectively, a signal ICLK3 is generated from the output signals b and d. Further, another signal ICLK1 is generated by dividing the output signal c and another signal ICLK2, which is the inverse of ICLK1, is generated. The VCO 102 then generates a normal clock signal 1 from ICLK1 and ICLK3, and generates a normal clock signal 2 from ICLK2 and ICLK3. In addition, when the frequency divider surrounded by a dashed line of FIG. 20 receives the normal clock signal 1 via the signal line c, it generates and furnishes a normal clock signal 3 as ICLK1.
Next, a description will be made as to the operation of the internal clock generating circuitry that is placed in test mode. FIGS. 22 and 23 are timing charts showing the waveforms of the plurality of clock signals applied to the circuitry and generated in the circuitry in test mode. In test mode, a high impedance is created between the input terminals Xin and Xout. The control signal A at a given level is applied to the selector 104 so that the selector 104 selects the plurality of test clock signals 1 to 3 as the plurality of internal clock signals 1 to 3. Under this condition, clock signals, as shown in FIG. 22, are applied to the input terminals Xin and Xout, respectively. The clock signal applied to the input terminal Xout is the same as the clock signal applied to the input terminal Xin under normal conditions. The same feedback control as that done under normal conditions is carried out to supply the voltage VCNT from the phase comparator to the voltage controlled delay circuit 105. In the voltage controlled delay circuit 105 to which the voltage VCNT is supplied, each group of transistors, which constitutes each of the plurality of inverters 111a to 111j, provides the same delay as provided by the VCO 102. Under this condition, when the circuitry receives a clock having the same frequency as the internal clock signal 1 by way of the input terminal Xin, the output signals b, c, d, e, axe2x80x2, bxe2x80x2, cxe2x80x2, dxe2x80x2, and exe2x80x2 from the respective stages of the voltage controlled delay circuit 105 are delayed with respect to the output signals a, b, c, d, e, axe2x80x2, bxe2x80x2, cxe2x80x2, and dxe2x80x2 by a given time delay, respectively, as shown in FIG. 23. In addition, each of the output signals b, c, d, e, axe2x80x2, bxe2x80x2, cxe2x80x2, dxe2x80x2, and exe2x80x2 is the inverse of each of the output signals a, b, c, d, e, axe2x80x2, bxe2x80x2, cxe2x80x2, and dxe2x80x2. The test clock generating circuit 106 receives the plurality of clock signals from the voltage controlled delay circuit 105 and then generates the plurality of test clock signals 1 to 3 using the same means as provided by the normal clock generating circuit 103, as shown in FIG. 23.
When it is necessary to hold each of the plurality of test clock signals at a given level in test mode, the prior art internal clock generating circuitry constructed as above can hold the levels of the plurality of test clock signals 1 to 3 by holding the level of the input clock signal applied to the input terminal Xin because the level of the clock signal furnished by each stage of the voltage controlled delay circuit 105 is held. FIG. 23 shows the waveforms of the plurality of clock signals applied to the circuitry and generated in the circuitry in test mode when the level of the input clock signal applied to the input terminal Xin is held.
A problem with prior art internal clock generating circuitry constructed as above is that it is necessary to apply a clock signal having the same frequency as one internal clock signal from outside the circuitry in order to generate a plurality of test clock signals respectively having the same frequencies as the plurality of normal clock signals generated and furnished by a feedback loop including a VCO, and the degree of difficulty in supplying the clock signal having the same frequency as one internal clock signal from outside the circuitry and hence generating the plurality of test clock signals is increased as the internal clock speed increases.
The present invention is proposed to solve the above problem. It is therefore an object of the present invention to provide internal clock generating circuitry capable of generating a plurality of test clock signals based on an input signal from outside the circuitry and stopping the generation of them even when the internal clock speed is high.
In accordance with one aspect of the present invention, there is provided internal clock generating circuitry comprising: a phase comparator for comparing the phase of a clock signal applied thereto from outside the circuitry with that of a feedback signal fed back thereto, and for generating a voltage corresponding to the difference between the phases of those clock signals; a voltage-controlled oscillator or VCO for generating a clock signal having a frequency corresponding to the voltage from the phase comparator; a normal clock signal generating circuit for generating at least one normal clock signal used for making an internal circuit operate under normal conditions from the clock signal from the VCO, and for generating and feeding the feedback signal back to the phase comparator; a test VCO for generating a clock signal having a frequency corresponding to the voltage from the phase comparator; a test clock signal generating circuit for generating at least one test clock signal used for testing the internal circuit from the clock signal from the test VCO; a selector for selecting either the normal clock signal generated by the normal clock signal generating circuit or the test clock signal generated by the test clock signal generating circuit, and for furnishing the selected clock signal to the internal circuit; and a control signal generating circuit for generating a control signal to stop the test VCO according to an input signal applied thereto from outside the circuitry.
In accordance with a preferred embodiment of the present invention, the test VCO includes a plurality of inverters connected in a loop, one of which can hold an output level according to the control signal from the control signal generating circuit.
Preferably, the test VCO includes a plurality of switching transistors each of which is connected between an output of a corresponding one of the plurality of inverters and a voltage source or ground. In addition, the control signal from the control signal generating circuit is applied to a control electrode of one switching transistor connected between the output of the one of the plurality of inverters that can hold an output level and the voltage source or ground, and a control electrode of each of other switching transistors connected between the output of each of other inverters and the voltage source or ground is connected to the voltage source or ground so that each of the other switching transistors is brought out of conduction.
In accordance with another preferred embodiment of the present invention, the control signal generating circuit receives one or more test clock signals so as to hold the levels of the one or more test clock signals, when testing the internal.
Preferably, the control signal generating circuit includes a selecting unit for enabling or disabling an input of at least one of the one or more test clock signals. To this end, the internal clock generating circuitry can further include a register for generating and furnishing a control signal to the selecting unit to cause the selecting unit to enable or disable the input of at least one of the one or more test clock signals.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.